FIG. 1 is a circuit diagram of a conventional output buffer circuit disclosed, for example, in Japanese Patent Application No. Hei. 7-176084, depicting the configuration of an input/output circuit of a semiconductor integrated circuit device equipped with a signal level converting function. In an output buffer of an interface circuit which is used between semiconductor integrated circuit devices that operate on different power supply voltages, such a half-latch type signal level converter as shown is used to convert the internal signal level from a low to a high voltage, and the output stage is formed by a push-pull circuit which has a buffer last stage made up of CMOS-structured inverter gates and NMOS-NMOS transistors.
Incidentally, what is intended to mean by the semiconductor integrated circuit device which possesses the signal converting function is a semiconductor integrated circuit device equipped with a function by which the signal voltage provided from a device operating on the power supply voltage in a large scale integrated circuit (LSI) is level converted for output to an external circuit which operates on a power-supply voltage different from that of the internal circuit, and a function by which a signal provided from a device operating on an external power-supply voltage different from the internal one is level converted to the signal voltage of the internal circuit for input thereinto.
In FIG. 1, reference numeral 1 denotes an input/output terminal; 2 denotes a control terminal; 3 denotes an input terminal; 4a and 4b denote first power-supply potential points to which a first power-supply voltage VDD1 is fed and second power-supply potential points to which a second power-supply voltage VDD2 is fed, respectively; 5 denotes ground potential points to which the ground potential GND is fed; 6 denotes an input/output control circuit; 7a and 7b denote a first converter circuit block and a second converter circuit block, respectively; and 8a denotes a buffer circuit. These circuit elements constitute an output buffer circuit 91a. Reference numeral 10 denotes an input buffer and 11 a static-shielding circuit.
To the input/output terminal 1 is connected an internal circuit via the input buffer 10. Connected further to the input/output terminal 1 via the output buffer circuit 91a are the control terminal 2 which is supplied with a control signal IN1 from the internal circuit and the input terminal 3 which is supplied with an output signal IN2 from the internal circuit.
The output buffer circuit 91a is composed principally of the input/output control circuit 6, the signal level converter circuit 7 and the buffer circuit 8a, and the control terminal 2 and the input terminal 3 are connected to the input/output control circuit 6. The input/output control circuit 6 outputs to the signal level converter circuit 7, and the signal level converter circuit 7 outputs to the buffer circuit 8a via connection points N13 and N23.
The input/output control circuit 6 and the first converter circuit block 7a forming the first half part of the signal level converter circuit 8 operate on the first power-supply voltage VDD1, which is also the power-supply voltage of the internal circuit, and the ground potential GND. On the other hand, the second converter circuit forming the second half part of the signal level converter circuit 7 and the buffer circuit 8a operate on the second power-supply voltage VDD2, which is generally higher in voltage level than the first power-supply voltage VDD1, and the ground potential. The first power-supply voltage VDD2 and the second power-supply voltage VDD2 are supplied via the power-supply potential points 4a and 4b, respectively, and the ground potential GND is supplied via the ground potential points 5.
A description will be given below of the cases where the control signal IN1 and the output signal IN2 that are applied to the control terminal 2 and the input terminal 3, respectively, are at the "H" level and at the "L" level.
When the control signal IN1 is at the "H" level, the output signal IN2 is at the "L" level and the signal level converter circuit 7 forces the connection points N13 and N23 to the "L" level (the ground potential GND) and the "H" level (the second power-supply voltage VDD2), respectively. As a result, transistors Q13 and Q14 of the buffer circuit 8a both turn OFF, making the buffer circuit 8a high-impedance relative to the input/output terminal 1. Hence, an external signal fed to the input/output terminal 1 is transmitted to the input buffer 10 with no loss.
On the other hand, when the control signal IN1 is at the "L" level and the output signal IN2 at the "L" level, the signal level converter circuit 7 forces either of the connection points N13 and N23 to the "L" level. As a result, the transistors Q13 and Q14 of the buffer circuit 8a turn ON and OFF, respectively, making the input/output terminal 1 "L" level.
And, when the control signal IN1 is the "L" level and the output signal IN2 at the "H" level, the signal level converter circuit 7 forces either of the connection points N13 and N14 to the "H" level. As a result, the transistors Q13 and Q14 of the buffer circuit 8a turn ON and OFF, respectively, making the input/output terminal 1 "H" level.
FIG. 2 schematically illustrates in section the transistors Q13 and Q14 forming the last stage of the buffer circuit 8a. Reference numeral 1 denotes an input/output terminal, 4b a second power-supply potential point, 5 a ground potential point, and N15 and N24 connection points. In P wells on a P-type semiconductor substrate connected to the ground potential point GND there are formed the NMOS transistors Q13 and Q14. The NMOS transistor Q13 has its drain electrode connected to the second power-supply potential point 4b, its gate electrode connected to the connection point N15, its source electrode connected to the input/output terminal 1 and its P well potential connected to the ground potential point 5. The NMOS transistor Q14 has its source electrode connected to ground potential point 5, its gate electrode connected to the connection point N24, its drain electrode connected to the output terminal 1 and its P well potential connected to the ground potential point 5.
FIG. 3 is a circuit diagram of another example of the conventional output buffer circuit, depicting the configuration of an input/output circuit of a semiconductor integrated circuit device equipped with the signal level conversion facility. Reference numeral 8b denotes a buffer circuit, which is a substitute for the buffer circuit 8a of the configuration shown in FIG. 1. More specifically, the buffer circuit 8b has a CMOS push-pull type output stage by replacing a PMOS transistor Q15 for the NMOS transistor Q13 in the final stage of the buffer circuit 8a and omits an inverter gate G18. Reference numeral 91b denotes the output buffer circuit.
FIG. 4 depicts in section the transistors Q15 and Q14 forming the final stage of the buffer circuit 8b. Reference numeral 1 denotes an input/output terminal, 4b a second power-supply potential point, 5 a ground potential point, N14 and N24 connection points, and Q14 and Q15 an NMOS and a PMOS transistor. In a P well on a P-type semiconductor substrate connected to the ground potential point GND there is formed the NMOS transistor Q14, which has its source electrode connected to the input/output terminal 1 and its P well potential connected to the ground potential point 5. On the other hand, the PMOS transistor Q15 is formed in an N well, and has its source electrode connected to the second power-supply potential point 4b, its gate electrode connected to the connection point N14 and its drain electrode connected to the input/output terminal 1.
With such a configuration, too, the circuit performs the same operations as described above in respect of FIG. 1. That is, when supplied at the gate with the "H" level or "L" level signal, the NMOS transistor Q14 and the PMOS transistor Q15 operate inversely to each other, but since the buffer circuit 8b of FIG. 3 does not have the inverter gate G18, no signal level inversion will occur and the both transistors will ultimately operate in the same fashion.
Accordingly, when the traditional output buffer circuit equipped with the signal level conversion facility performs its normal output operation, the pair of potentials at the connection points N13 and N23 assumes any one of the three states ("H" level, "H" level), ("L" level, "L" level) and ("L" level, "H" level) as in the two examples described above.
However, in the case where the first power-supply voltage VDD1 has not been supplied in the initial state in which the second power-supply voltage VDD2 has already been supplied, values of respective parts in the signal level converter circuit 7 are not unequivocally determined. For example, in FIG. 1 the pair of potentials at the connection points N13 and N23 can enter the state ("H" level, "L" level). This brings about a situation where the MOS transistors Q13 and Q14 (Q15, Q14 in FIG. 3) both turn ON simultaneously, giving rise to a problem that an unnecessary current, i.e. a through current flows between the second power-supply potential point 4b and the ground potential point 5.
The present invention is intended to solve such a problem as referred to above, and has for its object to provide an output buffer circuit of a circuit configuration that would reset the state in which a potential is provided corresponding to logic of flowing a through current across transistors forming the final stage of the output buffer circuit.